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Twincreeks's avatar
Twincreeks
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5 years ago
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What is the highest data rate with Cyclone 10 GX pins in diff SSTL 1.2 V?

I hope to use a Cyclone 10 GX device to transmit data. The datasheet specifies the highest data rate to be 1.434 Gbps. It is not an issue for LVDS standard with th...
  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    5 years ago

    Hi Twincreeks

    This is the understanding we got from the backend team. Since there are various factors that might affect the maximum performance of different IO standard of GPIO, we do not guarentee the max performance number, which is also the reason it is not listed in the specification documentation.

    Thanks.

    Eng Wei

EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Twincreeks

This is the understanding we got from the backend team. Since there are various factors that might affect the maximum performance of different IO standard of GPIO, we do not guarentee the max performance number, which is also the reason it is not listed in the specification documentation.

Thanks.

Eng Wei

  • GLees's avatar
    GLees
    Icon for Contributor rankContributor
    5 years ago

    In other words, Intel is saying they will not give you ANY indication of the maximum achievable performance of an I/O standard. You have to figure this out for yourself. This is complete nonsense. At the very least they should point to one or more reference designs and tell you what the maximum performance was under THOSE conditions. At least that way you have SOME idea of what MIGHT be achievable. Yet another reason for migrating to Xilinx..........