Forum Discussion
New ContributorWhat is the highest data rate with Cyclone 10 GX pins in diff SSTL 1.2 V?
Hi Twincreeks
This is the understanding we got from the backend team. Since there are various factors that might affect the maximum performance of different IO standard of GPIO, we do not guarentee the max performance number, which is also the reason it is not listed in the specification documentation.
Thanks.
Eng Wei
Frequent ContributorHi there
The maximum data rate for general purpose I/O standards is not published as it is depends on design and system specific factors. You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
There is only LVDS SERDES IP available in Quartus. Thanks.
Eng Wei
New ContributorHi Eng,
Thanks.
In another post https://community.intel.com/t5/Programmable-Devices/Does-Cyclone-10-GX-general-purpose-support-1-434-Gbps/m-p/1287593#M80166,
Asked: Does Cyclone 10 GX general-purpose support 1.434 Gbps differential SSTL-12?
Answered: Yes, it will be the same.
It seems that this answer is not well-founded.
Best regards,
Twincreeks
- EngWei_O_Intel
Hi Twincreeks
This is the understanding we got from the backend team. Since there are various factors that might affect the maximum performance of different IO standard of GPIO, we do not guarentee the max performance number, which is also the reason it is not listed in the specification documentation.
Thanks.
Eng Wei
GLeesContributor
In other words, Intel is saying they will not give you ANY indication of the maximum achievable performance of an I/O standard. You have to figure this out for yourself. This is complete nonsense. At the very least they should point to one or more reference designs and tell you what the maximum performance was under THOSE conditions. At least that way you have SOME idea of what MIGHT be achievable. Yet another reason for migrating to Xilinx..........
