Forum Discussion
Deshi_Intel
Regular Contributor
4 years agoHi,
Pls see my reply below.
- The line rate at the input can change at any time, and there is probably a flag that indicates the input is not locked anymore.
- Yes, NativePHY IP does has "cdr_lockedtodata" status signal to indicate whether Receiver channel CDR loose lock or not
- What is the fastest way to figure out what the new line rate is to reconfigure the transceiver to run at that line rate ?
- There is no so called fastest way as this is typically handled on high level IP protocol layer and not by physical layer.
- Your high level application first need to decide what data rate you want to run
- then put the FPGA receiver channel into reset, reconfigure the transceiver receiver channel to support new data rate
- finally new data rate input data only come in to the receiver channel again
Thanks.
Regards,
dlim