Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorWhat is the correct input voltage of PERST# from PCIe slot?
Hello, all!
I am confused - what is the correct input voltage of PERST# from PCIe slot? PERST# is named as pcie_perstn in CYCLONE IV GX reference boards and is set to different voltages. 1). In .qsf for Cyclone IV GX Transceiver Starter Kit pcie_perstn input is set as 2.5 V: set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_perstn 2). In .qsf for Cyclone IV GX FPGA Development Kit pcie_perstn input is set as 1.8 V: set_instance_assignment -name IO_STANDARD "1.8 V" -to pcie_perstn In my design IO voltages 1.8 V and 2.5 V are not used and therefore I don't want to assign the whole bank to 1.8 V or 2.5 V only because pcie_perstn is either 1.8 V or 2.5 V. In my design all IO voltages are assigned as 3.3-V LVCMOS. Can I assign pcie_perstn to 3.3-V LVCMOS like this: set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pcie_perstn ? Obviousely the answer could be found in PCI Express Card Electromechanical Specification. Here what it says about PERST# (pcie_perstn ): https://www.alteraforum.com/forum/attachment.php?attachmentid=7985 Do I understand it correctly, that PERST# (pcie_perstn ) Input high voltage on the PCIe slot and thefore on the CYCLONE IV GX input pin is really between 2.0 V and at least 3.3 V and I can safely assign PERST# (pcie_perstn ) to 3.3-V LVCMOS like this: set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pcie_perstn ? If Yes, then why in the Cyclone IV GX FPGA Development Kit PERST# (pcie_perstn ) is assigned to 1.8 V which seems to be too low to accept PERST# (pcie_perstn )?13 Replies
Altera_ForumI agree with your assessment. The PCIe CEM (PCI_Express_CEM_20.pdf) indicates that PERST# is a 3.3V signal.
Don't always "believe" what you see implemented on an evaluation kit, since they are for "evaluation" only :) Cheers, Dave- Altera_Forum
Thank You, Dave.
But feeding 3.3V PERST# from PCIe slot to a Cyclone IV GX pin assigned to 1.8 V bank could damage it? - Altera_Forum
It's helpfulful to read the dev kit schematic thoroughly.
I see PCIE_T_PERSTn, the 3.3V reset signal from PCIe connector and PCIE_PERSTn, the 1.8V signal going to the FPGA, and a MAX3378 level converter inbetween. Nevertheless, 3.3V won't damage the I/O cells of a 1.8V bank. - Altera_Forum--- Quote Start --- But feeding 3.3V PERST# from PCIe slot to a Cyclone IV GX pin assigned to 1.8 V bank could damage it? --- Quote End --- No. If you read the Cyclone IV handbook "Table 1–2. Maximum Allowed Overshoot During Transitions over a 10-Year Time Frame for Cyclone IV Devices" indicates that you would not damage the input. However, since the logic levels for 1.8V are not the same as those of 3.3V, so there is a logic incompatibility. In the case of the PERST# signal, its driven low, and most likely pulled high by a pull-up. How "high" that pull-up will get will depend on the input buffer setting on the 1.8V logic input. Measure it, and see what the voltage is. Lets say the logic high was clamped to 1.8V plus a diode, i.e,, about 2.5V. That logic level is then above a LVTTL VIH(min) = 2.0V, so any other devices on the bus would see it as a logic high. Using a 1.8V input was a poor choice on that board. There are plenty of 3.3V to 1.8V level translation devices that would have been appropriate. This is not the first design error I've seen on Altera kits. I've seen many cases of 5V logic levels on FPGA or CPLD I/O pins, eg., many of the LCD displays that ship with the kits. Cheers, Dave
- Altera_Forum--- Quote Start --- It's helpfulful to read the dev kit schematic thoroughly. I see PCIE_T_PERSTn, the 3.3V reset signal from PCIe connector and PCIE_PERSTn, the 1.8V signal going to the FPGA, and a MAX3378 level converter inbetween. Nevertheless, 3.3V won't damage the I/O cells of a 1.8V bank. --- Quote End --- Thank You , FvM! I didn't look into the Cyclone IV GX FPGA Development Kit schematic this time, just looked into the .qsf file. I couldn't think , that Altera used name PCIE_T_PERSTn for the signal from PCIe slot, I thought it was a direct connection and PCIE_PERSTn was coming directly directly from the PCIe slot. OK, use of level converter gives me an answer, that I wanted to know - that PERST# is really 3.3 V and I can safely connect it to 3.3 V bank.
- Altera_Forum
But maybe there is a strong reason, that Altera even decided to use a dedicated level converter in order to put PERST# into 1.8 V bank?
- Altera_Forum--- Quote Start --- But maybe there is a strong reason, that Altera even decided to use a dedicated level converter in order to put PERST# into 1.8 V bank? --- Quote End --- The bank most likely needed to be 1.8V to support a memory interface. The PCI RST# signal can be assigned to any pin on the FPGA, since its an asynchronous reset signal. As FvM commented above, read the schematic, most of these types of questions should be obvious by reviewing it, along with the FPGA pin planner view (to see the pins assigned in each bank). Cheers, Dave
- Altera_Forum--- Quote Start --- The bank most likely needed to be 1.8V to support a memory interface. The PCI RST# signal can be assigned to any pin on the FPGA, since its an asynchronous reset signal. Cheers, Dave --- Quote End --- I agree, but what makes developers ( Altera and others ) to route PCI RST# not to obvious 3.3 V bank of Cyclone IV GX, but to 1.8V bank ? Here is anoher development card ( http://devboards.de/en/home/boards/product-details/article/db4cgx15/ ) , which routes PCI RST# ( for strange reason they named it as PowerGood ) directly to 1.8 V Bank 7 of EP4CGX15. Here are screenshots to prove it: https://www.alteraforum.com/forum/attachment.php?attachmentid=7989 https://www.alteraforum.com/forum/attachment.php?attachmentid=7988 https://www.alteraforum.com/forum/attachment.php?attachmentid=7987
- Altera_Forum--- Quote Start --- I agree, but what makes developers ( Altera and others ) to route PCI RST# not to obvious 3.3 V bank of Cyclone IV GX, but to 1.8V bank ? --- Quote End --- You do not have to route the signal to a 3.3V bank. The PCI RST# signal is an input to the FPGA. So long as the FPGA resets its PCIe end-point when reset is asserted, the implementation details are subject to the designer's implementation constraints. Given that the designers had to use 1.8V for DDR memory interfaces, its reasonable to use spare I/O pins for miscellaneous inputs, eg., the 3.3V reset after passing it through a level translator. Cheers, Dave
- Altera_Forum--- Quote Start --- Given that the designers had to use 1.8V for DDR memory interfaces, its reasonable to use spare I/O pins for miscellaneous inputs, eg., the 3.3V reset after passing it through a level translator. Cheers, Dave --- Quote End --- If this is the only reason and there are no other hidden reasons for routing PCI RST# to 1.8 V banks of Cyclone IV GX, then that brings me calm. :) This is my first project with Altera and PCIe and want to be sure , that everything is verified and no questions left unresolved. Dave and FvM, thank You again for Your assistance.
