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Altera_Forum
Honored Contributor
Honored ContributorWhat is the best way to generate multiple clocks with minimum jitter and delays?
Hi, I have to generate several clocks on Arria 10 SoC board. The clocks and their applications are as follows: 3GHz clock: for clocking external ADC to sample the incoming data, and receive...
Altera_ForumHonored Contributor
Honored ContributorGenerating a clock signal on transceiver pins might be possible under circumstances by sending a constant 01010101 sequence. A bit unusual though.
My general concern is that FPGA PLL clocks have relative high jitter, not well suited as ADC clock if you have performance requirements for the ADC output.
