Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

What is the best way to generate multiple clocks with minimum jitter and delays?

Hi, I have to generate several clocks on Arria 10 SoC board. The clocks and their applications are as follows: 3GHz clock: for clocking external ADC to sample the incoming data, and receive...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Generating a clock signal on transceiver pins might be possible under circumstances by sending a constant 01010101 sequence. A bit unusual though.

My general concern is that FPGA PLL clocks have relative high jitter, not well suited as ADC clock if you have performance requirements for the ADC output.