What is the best way to generate multiple clocks with minimum jitter and delays?

No, there is no external clock here. I want to generate three synchronized clocks at frequencies 150MHz, 1.5GHz, and 3GHz; the first two would be used at the Arria 10 Transceiver PHY to send data at 3Gbps (1.5GHz), while the last one (3GHz) would be used to sample the received analog signal at external high-speed ADC. My question here is that how can I generate these three clocks such that they are synchronized. The synchronization is important to get the time of flight of the transmitted signal, which is essential for the application.

Please let me know if you have any suggestions on how can I generate these clocks. I have tried several options (I have described them above) using the PLLs available for Arria 10 SoC, but they did not work for me.