What is best to do to test a custom circuit with large amount of data?

Question

Hi everyone,

I have implemented a electron-beam data decompression circuit in verilog-hdl. I need to run it and benchmark it with large amount of data (over 200 mega-bytes). I don't have any non-free IP so I can only use Altera University Program SD-Card and DDR2 memory IP.

What do you guys think is the best way to benchmark my circuit?

The solution I've come up with is to use Qsys to build a system with Nios II (Avalon MM Master), SD-Card Controller (Avalon MM Slave), DDR2 Controller (Avalon MM Slave), and my electron-beam data decompression circuit (Avalon MM Master). I will write a C program to have Nios II control the SD-Card controller to read the large amount of benchmark data into DDR2 memory. Then Nios II will inform my electron-beam data decompression circuit that the data in DDR2 memory is read. After that, my electron-beam data decompression circuit will read the data from the DDR2 memory and perform decompression. Then my electron-beam decompression circuit will write the benchmark result into on-chip memory, and then the Nios II processor will read the benchmark result from the on-chip memory and save it into a file in SD-Card.

This is the first time I use Qsys to build a SoC system. So I have to find out how to encapsulate my electron-beam data decompression circuit into a Avalon MM Master interface.

Or can you guys please suggest better/easier solutions to build a system to test my decompression circuit or point out the errors/difficulty/challenge in my solution?

Thanks a lot!!

altera_forum · Answer

This sounds extremely complex. Why cannot you just take ModelSim? Verilog has file read function.

altera_forum · Answer

I did benchmark my circuit in ModelSim using the verilog file read function. But my professor said that the benchmark results of ModelSim is only a simulation benchmark results, not emulation benchmark results on FPGA chip. Since we are writing a IEEE TCAS1 (Transactions on Circuits and Systems I) paper, to increase our chance of our paper getting accepted, I thought it would be best to obtain all benchmark results from FPGA chip.

altera_forum · Answer

I forgot the mention that my electron-beam data decompression circuit has to run at 200 MHz. So the input data rate into the decompression circuit is 200 Mega-bit per second. I am not sure if the Altera University Program SD-Card control can supply that kind of data rate. Anyway, I need to use some kind of file system, because I have like over 9000 benchmark files. Thus I need to use Nios II processor.

altera_forum · Answer

How are you going to exclude Nios II cycles used for some internal operations from your benchmark?

I suggest you following setup: you take Nios II, custom DMA, DDR2 and the module to be tested. When you start the benchmark, Nios II copies flash content to RAM and starts DMA and a counter. Your custom DMA feeds the tested module directly with data from DDR2. When tested module finishes the job, it sends an interrupt. Nios II stops a counter and prints the result..

altera_forum · Answer

Thank you for your suggestions.

My circuit is designed to count the clock cycles when a complete compressed file is being loaded into the circuit.

The flash memory on DE4 has only 64mb. Because I have large amount of data to perform benchmark (> 9000 files) I need some kind of file system. FAT-16 of the SD-Card Core should allow me to use 2gb SD-Card. I never thought about using custom-DMA and interrupt to test my circuit. I will look into the designs.

Thanks a lot!!

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What is best to do to test a custom circuit with large amount of data?

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