Forum Discussion
2 Replies
- Altera_Forum
Honored Contributor
The SCFIFO core doesn't support mixed width as far as I can tell.
The DCFIFO does however, but that has separate read and write used word signals (wrusedw and rdusedw). So they will represent the width of the respective ports. - Altera_Forum
Honored Contributor
Sorry, I corrected the question. You have answered the question. Basically, in the code I was looking at, at top level there was just one usedw signal and not two. However, looking deaper into the code I have found that a DCFIFO is being used and one of the usedw is not connected to the module port.