What are the multi cycle constraints reference launch and latch edges

default launch edge is just any edge. Timequest does not check every edge in a dynamic way but it is static analysis so it looks at a path and views any edge of source register clock as a launch.

for setup check, latching edge is then the first edge at destination register following the launch edge at source register as you mentioned(for this edge definition the final delays inserted are zeroed but come in action at timing report).

for hold check, again your are right, it is the nearest edge at destination register before the launch at source register.(again assuming delays of zero)