What are the multi cycle constraints reference launch and latch edges

Hello,

can anybody tell me what the default launch and latch edges for multi cycle constraints are?

Here is a timing diagram which I use to visualize the start/end setup/hold relationships for multi cycle constraints:

https://www.alteraforum.com/forum/attachment.php?attachmentid=8094

The clock constraints for this example could look like this:

set_time_format -unit ns -decimal_places 3
set t_period_50mhz 20.000
set t_period_100mhz 10.000
create_clock -name clk_50mhz -period ${t_period_50mhz}
create_clock -name clk_100mhz -period ${t_period_100mhz} -waveform {5 10}

In this example the first launch edge would be at t0 (rising edge to rising edge transfers) and the first latch edge would be at t0 + 5 ns.

How are the default setup and hold relationships determined?

Can I assume for the setup relationship the following?:

• Default launch edge = the first launch edge which comes after >= t0 (in this case the first launch edge would be at t0)

• Default latch edge = the first latch edge which comes after the first launch edge, in this case > t0

Now for the hold relationship:

• Default launch edge = second launch edge which comes after >= t0 (in this case the second launch edge would be at t0 + t_period_50mhz)

• Default latch edge = first latch edge which comes at the same time or just before the second launch edge (the second hold launch edge in this example is at t0 + t_period_50mhz and the nearest latch edge before or equal would be at t0 + 1.5 * t_period_100mhz)

Regards

Martin