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omar_ibrahim
New Contributor
New Contributorweird behaviour of fitter in quartus for SDRAM project
I've been working on SDRAM controller project using verilog using cyclone v 5cefa5f23i7.
The SDRAM have four bank , 3 cas latency and 166 Mhz clock.
I start design with a goal of having lowest po...
AdzimZM_Altera
Regular Contributor
Regular ContributorWe do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
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