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omar_ibrahim's avatar
omar_ibrahim
Icon for New Contributor rankNew Contributor
3 years ago

weird behaviour of fitter in quartus for SDRAM project

I've been working on SDRAM controller project using verilog using cyclone v 5cefa5f23i7. The SDRAM have four bank , 3 cas latency and 166 Mhz clock. I start design with a goal of having lowest po...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi omar_ibrahim,


Thank you for using Intel Community.


I'm not familiar with your module and not much I can help you here unless you're using Intel EMIF IP.

I can provide the Example Design for the EMIF IP later.


Regards,

Adzim