Waveform simulation no results！

VHDL code is not wrong ,but when i create do not get the results of simulation waveform file.somewhere i malke a mistake !! can you help me ?

library ieee;

use ieee.std_logic_1164.all;

entity counter10 is

port (clk: in std_logic;

digit : out std_logic );

end counter10 ;

architecture counter10 of counter10 is

begin

process (clk)

variable temp:integer range 0 to 10;

begin

if(clk'EVENT AND clk='1')then

temp:= temp+1;

if (temp=10)then temp:=0;

end if ;

end if ;

end process;

end counter10 ;