Forum Discussion
New ContributorVREFB pin in Cyclone V
Hello,
Since it is mentioned in the Pin Connection Guideline that the pin needs to connect either GND or VCCIO if not used, then I am afraid you can't leave it floating.
Although I can't confirm with you that this is the cause of those faulty JTAG pins, I guess what will happen to the pin if left floating is the output of the buffer logic will be undefined since those pins are voltage-reference pins. It means that the pin should be connected to a valid logic for the hardware to work as expected.
Regular ContributorHello,
Since it is mentioned in the Pin Connection Guideline that the pin needs to connect either GND or VCCIO if not used, then I am afraid you can't leave it floating.
Although I can't confirm with you that this is the cause of those faulty JTAG pins, I guess what will happen to the pin if left floating is the output of the buffer logic will be undefined since those pins are voltage-reference pins. It means that the pin should be connected to a valid logic for the hardware to work as expected.
- HiOh
I appreciate your response. I understand that it is indeed difficult to accurately determine the consequences of performing actions that are not recommended. First, I will address the floating state of the input pins. Thank you for your advice.
FvMSuper Contributor
Hi,
I wonder what "faulty JTAG pins" actually means? Does it mean JTAG doesn't work at all, or just seeing unreliable operation?
I experienced some cases where JTAG signals, specifically TCK, suffered from crosstalk of other signals on the board. Problem is relative large driver impedance of some JTAG adapters, e.g. classical USB Blaster which can lead to bad JTAG signal quality.
I won't expect actual problems from floating VREF pins, but I have it connected to GND in all Cyclone V designs, so it's only an educated guess.
Regards
Frank- HiOh
Sorry for the delayed response.
"Faulty JTAG pins" refers to physical faults. Specifically, the symptoms are as follows: TDI-N5 5.3Ω (short), P3.3-TCK 5.2Ω (short), TCK-N5 376Ω (short), P3.3-TDI 8.2Ω (short), TDO-N5 1.8Ω (short).
I suspected a potential difference between the GND of the JTAG cable and the GND of the board, or ESD, but I have not been able to identify the cause so far. Therefore, I wanted to confirm whether the open VREF could be the cause.
Regards
