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Altera_Forum's avatar
Altera_Forum
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8 years ago

voltage level of GPIO pins of Cyclone 10 GX

Hi all, I have recently encountered a problem while working with a design that has alot (4 to 5) 3.3 v I/O peripherals to be interfaced with Cyclone 10 GX FPGA. The design challenge is the FPGA...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Hey grateful for the replies!!

Even I was contemplating to either come down to either MAX II or MAX 10.Now MAX 10 looks a better option .

I also wanted to clear one more doubt.As I have already told my PCI peripheral uses around 70 signals and keeping voltage translator might introduce skew among the signals....why not go for an option of synchronizers in fpga? Is the implementation of synchronizer in fpga feasible?