VHDL timer

hi

this is exactly what happened...

Assuming the sensor output has no glitches, it still can't drive the enable signal or the result register directly, because it's asynchronous to the system clock. It must be synchronized first, otherwise you'll get a certain amount of incorrect readings.

I also would like to add a note.

yes.

do u mean enternal clk on de2 kit?

no, the clock is always a clock input

ok....i think it's ok

I just saw you want VHDL.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity count is
    port
    (
        clk        : in std_logic;
        reset    : in std_logic;
        enable     : in std_logic;
        q        : out integer range 0 to 255
    );
end entity;
architecture rtl of count is
begin
    process (clk)
        variable   cnt    : integer range 0 to 255;
    begin
        if (rising_edge(clk)) then
            if reset = '1' then
                -- Reset the counter to 0
                cnt := 0;
            elsif enable = '1' then
                -- Increment the counter if counting is enabled
                cnt := cnt + 1;
            end if;
        end if;
        
        -- Output the current count
        q <= cnt;
    end process;
end rtl;

From what I read the circuit will measure the number of clock pulses.

module counter
(
    clk,
    reset,
    result,
    ena
);
    input clk;
    input reset;
    input ena;
    output  result;
    reg  result;
    always @(posedge clk or posedge reset)
    begin
        if (reset) 
            result = 0;        
        else if (ena) 
            result = result + 1;
    end
endmodule