VHDL syntax Help

Hi Folks, I am relatively new to this VHDL lark and I have a quick question which I suspect is rather simple when you know how. I wish to code the following:

val1 is a STD_LOGIC_VECTOR(31 downto 0)

val2 is a STD_LOGIC_VECTOR(31 downto 0)

val3 is a STD_LOGIC_VECTOR(7 downto 0)

I wish to subtract val2 from val1 and put the result in val3. i know that the result will always be 8bit:

so i need something like:

val3 (7downto 0) <= STD_LOGIC_VECTOR(unsigned(val1(31 downto 0) - unsigned(val2(31 downto 0));

Now i know i need to 'slice the arithmetic operation as it gives me a 31 downto 0 size result, but where do i do the 'cast/slice' down to the correct width? I have tried a few arrangements and cant seem to get it right!

many thanks in advance

de Boogle