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Altera_Forum
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13 years ago

VHDL syntax Help

Hi Folks, I am relatively new to this VHDL lark and I have a quick question which I suspect is rather simple when you know how. I wish to code the following: val1 is a STD_LOGIC_VECTOR(31 down...
Altera_Forum's avatar
Altera_Forum
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13 years ago

As shown in a recent thread, Quartus 12 supports a special syntax where you append a slice specification to the conversion function, please review the discussion. IMHO it's not based on specified VHDL syntax and should be used with care.

http://www.alteraforum.com/forum/showthread.php?t=37199

The regular VHDL way to use an auxilary signal/variable is also discussed in the thread.