VHDL state to entity

add an output port with your favorite name, then

curr_state_out <= curr_state;

This should keep your customer happy.

Hi kaz,

This is throwing error. I had already tried this.

The error is copied below,

Error-[SEQSTMTASSIGNTYPE] Type mismatch

../dut/state_machine.vhd, 33

SYNTH

outp_state <= cur_state;

^

The assignment statement target data type does not match the source data

type. The target data type is 'Anonymous subtype of STD_LOGIC_VECTOR' and

is declared by 'PACKAGE IEEE.STD_LOGIC_1164'. The source data type is

'STATE' and is declared by 'ARCHITECTURE SYNTH'.

"../dut/state_machine.vhd": errors: 1; warnings: 0.

This occurs because our state variable is user defined and ouptut port is std_logic_vector.

The state definition is copied below;

type state is (IDLE, ST1, ST2, ST3, ST4,ST5, ST6, ST7);
signal cur_state, nxt_state : state;

Any idea to override this or any convesion function.

Regards,

freak

Hi,

Good point. There might be some of those special tool statements to do that(Only FvM knows those secrets) but if it is me I will regenerate a bit of logic:

case cur_state is

when idle => out_p <= "000";

when s1 => out_p <= "001";

...etc.

i.e. you convert it to numerical value onto std_logic_vector.

Regards

CurrentStateOut : out std_logic_vector( ceil(log2( number of states )) - 1 downto 0) ;
---
CurrentStateOut <= std_logic_vector( to_unsigned( state'pos(curr_state) ,  
                               ceil(log2( number of states )) ) ;

You have to replace the ceil(log2( number of states )) in the port declaration by a fixed number as the size of 'state' is only defined until later in the architecture section.

If the output is only required for simulation or documentation purposes you could define the output port as a natural:

CurrentStateOut : out natural ;
...
CurrentStateOut <= state'pos( curr_state) ;

simple, and you don't have to modify the code in case the 'state' definition changes during the design. The only drawback is that the natural is represented as a 31-bit vector, so you may want to restrict the range of the natural.

Thanks JosyB,

In layman terms like myself I believe you mean:

port declaration:

CurrentStateOut : out std_logic_vector(2 downto 0);

then in assignment section:

CurrentStateOut <= std_logic_vector(to_unsigned(state'pos(curr_state),3));

Hopefully that will do if tool support doesn't get in the way.

Sorry if I sounded like a preacher:)

I verified the solution in QII 9.1SP2 before committing the post. Attributes are well specified in the VHDL LRM so I don't think that ModelSim will choke on it. (if it does tell me)

Using the state'pos attribute is in fact the most reasonable way.

Alternatively, you can also use the state type in the entity interface, you get a bit vector according to the state machine encoding, one-state-hot state by default. The type has to be defined in a package.

P.S.: In terms of logic effort, the pos attribute does the same as decoding the states to numbers, as kaz suggested. The internal representation of the state variable will be still one state hot.

Hi FvM,

Can you please provide an example.

One more thing, Is natural data type synthesizable. ?

Regards,

freak

Hi vlsi_freak,

But Josyb answered you, I simplified his post and FvM endorsed it.

Regards

The code below looks to be working,

CurrentStateOut : out natural ;
CurrentStateOut <= state'pos( curr_state) ;

The below code is giving out error,

CurrentStateOut <= std_logic_vector(to_unsigned(state'pos(curr_state) ,3));

Is data dype 'natural' can be synthesized.