VHDL robot design not working

I see the Rst problem now and it was supposeto be ns and ms... but still no waves?

 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use std.textio.all;
--use ieee.std_logic_textio.all;
------------------------------------------------------------------------------
entity tb_pwm is
end entity tb_pwm;
------------------------------------------------------------------------------
architecture arc_tb_pwm of tb_pwm is
  signal Clk : std_logic             := '0';  -- 
  signal Rst : std_logic               := '0';  -- 
  signal Sw  : std_logic_vector  (2 downto 0):= "000";    -- 
  signal Enable : std_logic      := '0';  -- 
  signal Pwm : std_logic;                     -- 
  signal Led : std_logic_vector(7 downto 0);  -- 
begin
  
  test : entity work.pwm
    
    port map (
      Clk  => Clk,  
      Rst  => Rst,  
      Enable => Enable, 
      Sw  => Sw,  
      Pwm  => Pwm,  
      Led  => Led );                              
  Clk <= not Clk after 10 ns;
  process
    
  begin
    wait until rising_edge(Clk);
    Enable <= '1';
      wait until rising_edge(clk);
   Sw(0) <= '1';
   Sw(1) <= '0';
   Sw(2) <= '0';
   wait until rising_edge(clk); 
   Sw(0) <= '0';
   Sw(1) <= '1';
   Sw(2) <= '0';
   wait for 0.1us;
      wait until rising_edge(clk);
   Sw(0) <= '0';
   Sw(1) <= '0';
   Sw(2) <= '1';
   wait for 0.1us;
      wait until rising_edge(clk);
      Enable <= '0';
   wait for 0.1us;
      wait until rising_edge(clk);
   wait for 0.1us;  
   Rst<= '0';
  end process;
end architecture arc_tb_pwm;