VHDL robot design not working

The problem is your reset it driven outside and inside the process, leading to rst beign 'X', and none of the internal counters get initialised to 0. Either remove the rst <= after 20ns; line or Rst <= '0' inside the process.

Signals can only be driven from one place.

Secondly - are you sure you meant wait for 100ms? that is 10 million clocks with the clock period you have chosen.

thirdly, you are holding the design in reset for the whole simulation.

numeric_std is the official IEEE standard library. std_logic_arith/unsigned are not a real standard, but they allow you to do maths on std_logic_vectors. std_logic_vectors were NOT meant to represent an integer, just a collection of bits. numeric_std contains an unsigned and signed type that do represent numbers. you cannot use numeric_std and std_logic_arith in the same file as they contain clashes.