VHDL robot design not working

Your right I changed the code a little.

 
library IEEE;
 use IEEE.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
Entity Pwm is
    Port (    Rst : In  std_logic;
              Clk : In  std_logic;
              Sw : In  std_logic_vector (2 downto 0);
              Enable : in std_logic;
              Led : out std_logic_vector (7 downto 0);
     Pwm : Out std_logic);
    
  attribute altera_chip_pin_lc: string;
  attribute altera_chip_pin_lc of Clk  : signal is "@N2";
  attribute altera_chip_pin_lc of Rst : signal is "@G26";
  attribute altera_chip_pin_lc of Led  : signal is "@AE23, @AF23, @AB21, @AC22, @AD22, @AD23, @AD21, @AC21";
  attribute altera_chip_pin_lc of Sw    : signal is "@N25,@N26, @P25";
  attribute altera_chip_pin_lc of Enable: signal is "@AE14";
  
end entity Pwm;
Architecture arc_Pwm of Pwm is
signal Counter : std_logic_vector (16 downto 0);
signal DC : std_logic_vector (16 downto 0);
signal Rd_led : std_logic_vector (7 downto 0);
begin
PwmReg: process (Clk,Rst,Sw)
begin
  if (Rst='1') then
    Counter <= (others=>'0');
    Pwm <='0';
    Led <= (others=>'0');
    Rd_led <= (others=>'0');
    DC <= conv_std_logic_vector(32678,17); --duty cycle 50%
  elsif rising_edge(Clk) then
 if (Enable='1') then
  if (Counter = 50000) then
   Counter <= (others => '0');
   if (Sw(0) = '1') and (Sw(1) = '0') and (Sw(2) = '0') then 
    Rd_led <= Rd_led + 1;
   elsif (Sw(0) = '0') and (Sw(1) = '1') and (Sw(2) = '0') then   
    Rd_led <= Rd_led - 1;
   end if;
   Led <= Rd_led;
  elsif (Counter < DC) then
   Counter <= Counter + 1;
   Pwm <= '1';
  else
   Counter <= Counter + 1;
   Pwm <= '0';
  end if;
 else 
  Pwm <= '0';
 end if;
end if;
end process PwmReg;
end architecture arc_Pwm;