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Honored Contributor
Honored Contributorvhdl querry
Hello Friends, I am new to VHDL and I have a couple of querries. Kindly help me out if possible - 1) If-else loop in VHDL. Now, what I understand is that VHDL code is synthesised into har...
Altera_ForumHonored Contributor
Honored Contributornot exactly... at each clock rising edge, if reset_phy_clk is 1 then your write req will be 0, and if it isn't you will shift the values between the write_req. This code is a shift register with a synchronous reset.
Compared to your description, t0 and t1 are the same clock cycle, and t2 is a clock cycle after.
