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Altera_Forum
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15 years ago

vhdl querry

Hello Friends, I am new to VHDL and I have a couple of querries. Kindly help me out if possible - 1) If-else loop in VHDL. Now, what I understand is that VHDL code is synthesised into har...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

library ieee;

use ieee.std_logic_1164.all;

entity 3-bit parity generator/checker is

port

(

c : in std_logic;

b : in std_logic;

a : in std_logic;

odd_out : out std_logic;

);

end 3-bit parity generator/checker;

architecture arc of 3-bit parity generator/checker is

signal result : std_logic;

begin

process (a, b, c)

begin

result <= a xor b xor c;

odd_out <= result;

end process;

end arc;

I compile this VHDL but got errors and don't know what wrong with this