Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

vhdl querry

Hello Friends, I am new to VHDL and I have a couple of querries. Kindly help me out if possible - 1) If-else loop in VHDL. Now, what I understand is that VHDL code is synthesised into har...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

To design 3-bit parity generator/checker that has three data inputs (A to C) and one odd parity output (odd_out). When the number of high level input is odd, odd_out is kept HIGH. Likewise, if the number of high level input is even, odd_out is LOW. The design of this generator is to be written in VHDL. Produce the truth table for this generator and treat C as the MSB.

--- Quote End ---

cool thanks