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Altera_Forum
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8 years ago

VHDL Port Mismatch Error

Hi Everyone, I have defined a component in my VHDL Flash file as shown in the Capture 1 attachment. And I have generated a Flash IP. The Flash is instantiated as shown in Capture 2. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Can you draw a block diagram of how you think everything is hooked up? It can helpmin understanding what is going on.