Honored Contributor
Honored ContributorThe problem with variables is, that they can represent hardware, as Tricky has shown, but they can be also purely virtual, removed during synthesis. This won't be a problem normally, but if arithmetic overflows and implicite type conversions "happen" to the data, the result may be difficult to predict.
--- Quote Start --- I already stated that I changed all my variables to type integer. So the only type conversion I am doing is for the outputs Xm and Ym. --- Quote End --- As already mentioned, I see a possible overflow and an implicite type conversion in Xc1 := (d4 - d2). The input is unsigned integer and the output signed integer. As previously discussed, there's a possible ambiguousity, because the integer subtypes are synthesized as signed and unsigned by the compiler. So the synthesized result may be different from expectable integer behaviour or ModelSim simulation. What to do? You can either complain about possible incorrect synthesis of integer subtypes by Quartus, or try to avoid these ambiguousities by a clearer typing.
