VHDL Numeric Type Conversion

the fact you are doing post synthesis simulation probably explains why they are not working. Quartus is probably converting everything to a signed number during synthesis, or you are showing them in the simulator as signed when actually they are unsigned.

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I do know the difference b/t variables and signals. I wanted to use variables because they don't represent HW and I don't have to wait for the clock to change them.

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This shows you clearly do not understand variables. Just because they are updated immediatly does not mean they do not represent hardware. At the very least, variables may represent a wire between one register to the next. And in some circumstances they can be used to instantiate anything a signal can.

Consider the following two bits of code. The first one has a single register between the input and output.

process(clk)
  variable v : std_logic;
begin
  if rising_edge(clk) then
    v := input;
    output <= v;
  end if;
end process;

Now this code:

process(clk)
  variable v : std_logic;
begin
  if rising_edge(clk) then
    output <= v;
    v := input;
  end if;
end process;

Now v represents an additional register in the pipeline, so there are 2 registers between the input and output instead of just 1.