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Yes, because they are variables. You can use signals to make them visible.
My previous comment about d1 to d4 is still valid, I fear.
To ask explicitely:
how do you load the values for d1 to d4? May be, but you possibly don't understand the side-effects of implicite type conversion during assignment. I think, this previous suggestion is quite reasonable.
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I do know the difference b/t variables and signals. I wanted to use variables because they don't represent HW and I don't have to wait for the clock to change them. I did try using signals before posting this thread, and got even more unexpected simulation results. But I haven't tried using signals since changing them all to integers. I'll give this a try.
Here's how I load the values for d1 to d4:
---
dst1, dst2, dst3, dst4 : in integer range 0 to dst_max;
valid1, valid2, valid3, valid4 : in std_logic;
...
if valid1 = '1' then
d1 := dst1;
-- same for d2, d3, d4
---
I already stated that I changed all my variables to type integer. So the only type conversion I am doing is for the outputs Xm and Ym:
Xm <= std_logic_vector(to_signed(-Xc, 20));
There are no type conversions for Xp and Yp, but they are incorrect. If there's a problem w/ d1 to d4, why are Xm and Ym correct, though I had to type convert Xc and Yc?
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