VHDL Numeric Type Conversion

I am doing a post-synthesis timing simulation using Quartus 9.1 native simulator.

I changed my d# variables from type natural to (unsigned) integer. They represent distances, so cannot be negative. I got rid of the intermediary variables Xc_* and Yc_*, but kept Xm and Ym as output SLVs. But I still get the same results:

d1 = 1955, d2 = 300000, d3 = 158100, d4 = 23456

Xp should be -138272, but is 430016

Yp should be 78072, but is -369448

Xm is 138272 (correct)

Ym is -78072 (correct)

Xc* and Yc* could not be displayed by the simulator

Here's my revised code snippet:

---

generic(dst_max : positive := 300000);

...

Xm, Ym : out std_logic_vector(19 downto 0);

...

variable d1, d2, d3, d4 : integer range 0 to dst_max;

variable Xc, Yc, Xc1, Yc1, Xp, Yp : integer range -dst_max to dst_max;

...

Xc1 := (d4 - d2);

Xc := Xc1/2;

...

Yc1 := (d3 - d1);

Yc := Yc1/2;

...

Xp := Xc; -- update previous center

Yp := Yc;

Xm <= std_logic_vector(to_signed(-Xc, 20)); -- move back to center

Ym <= std_logic_vector(to_signed(-Yc, 20));

---

I don't understand how Xp and Yp have the unexpected simulation values while Xm and Ym have the correct simulation values, when both are representations of Xc and Yc.