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There is nothing here to show a problem. Are you sure the problem isnt elsewhere?
Out of interest, why do you do so many conversions? If this is not the top level, why not just leave all the ports as integers?
Also. If you want to divide by 2, do a divide by 2. The synthesisor will recognise it as a right shift:
Yx_sv <= Yx_sc1/2;
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The problem is that Xp and Yp are not simulated as expected, while Xm and Ym are. Both are derived from Xc and Yc as my previous code snippet shows:
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Xp := Xc; -- update previous
Yp := Yc; -- Xp and Yp DO NOT SIMULATE CORRECTLY
Xm <= std_logic_vector(to_signed(-Xc, 20)); -- move
Ym <= std_logic_vector(to_signed(-Yc, 20)); -- Xm and Ym SIMULATE CORRECTLY
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The previous coordinates Xp and Yp are needed if the current coordinates Xc and Yc are invalid.
This entity is not the top level, but Xm and Ym will be output pins at the top level. If I have them as output integers at this level, how do I read them to convert them to SLV's at the top level? Since you can't read outputs, can I have them as buffer integers at this level?
The synthesizer really will recognize the divide by 2 as a right shift? Is this true for all powers of 2? I thought division was a very costly operation.
Here's the simple math I wanted to implement:
Xc = (d4-d2)/2 = (23456-300000)/2 = (-276544)/2 = -138272
Xp = Xc = -138272
Xm = -Xc = 138272
I subtyped and range-limited my variables to reduce the bits/LE's used for synthesis.
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