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So you mean, (d4-d2) will get the correct numeric value? I'm not sure from which type property this could be derived. Actually, integer types are converted to signed and unsigned before synthesis, so I fear, the
subtype doesn't mean anything here. Furthermore, the bit width is increased by one in the assignment.
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I was refering the RTL level simulation, rather than post synthesis. But yes, Quartus may keep d4 and d2 as an unsigned, and so when the subtraction occurs it may underflow before asignment into the signed variable.
The safest way around this may be to keep everything in the same type (integer or signed), rather than constant changing from natural (which quartus may treat as an unsigned when converted to bits) to signed.
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