Forum Discussion

CLa_R's avatar
CLa_R
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

VHDL multiple asynchronous signal handling

Hi everyone, to realize an asynchronous project, I would need to manage different signals and understand when they change state, both from 0 to 1 and from 1 to 0. The change from these signals sho...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Could you check with .vhd file generated from .bdf file?

Open .bdf file( as designed in previous post) in Quartus & then,

"File" Menu->"Create/Update"->"Create HDL design file from current file(VHDL",

Regards,

Vikas