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CLa_R
Occasional Contributor
Occasional ContributorVHDL multiple asynchronous signal handling
Hi everyone, to realize an asynchronous project, I would need to manage different signals and understand when they change state, both from 0 to 1 and from 1 to 0. The change from these signals sho...
CLa_ROccasional Contributor
Occasional ContributorIt is possible to make a edge detector in VHDL? I think that It can to resolve the problem.
The Edge detector is a circuit like this:
Can I make it in VHDL?
I try with:
process (myInput)
begin
If (not (not myInput)) xor myInput = '1' then
--Edge detect!
end if;
end process;but this code do not compile/work (Error (10476): VHDL error at Control.vhd(90): type of identifier "MyInput" does not agree with its usage as "boolean" type)
