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CLa_R's avatar
CLa_R
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

VHDL multiple asynchronous signal handling

Hi everyone, to realize an asynchronous project, I would need to manage different signals and understand when they change state, both from 0 to 1 and from 1 to 0. The change from these signals sho...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

if possible please provide the project file, that will help us to better support.

if you don`t want to share it in community, you can use "My Messages" option to share with me.

Regards,

Vikas

  • CLa_R's avatar
    CLa_R
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    The basic problem is that I would like to implement the 2-phase handshake protocol.

    For this reason, I need to understand when a signal changes state.

    Is it possible to capture an event that indicates that the signal has changed its logic level?