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CLa_R's avatar
CLa_R
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

VHDL multiple asynchronous signal handling

Hi everyone, to realize an asynchronous project, I would need to manage different signals and understand when they change state, both from 0 to 1 and from 1 to 0. The change from these signals sho...
CLa_R's avatar
CLa_R
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Can I use this code? It is correct?

process (signal_1, signal_2)
begin
 
if signal_1 = '0' or signal_1 = '1' then
signal_out <= '0'
end if;
 
if signal_2 = '0' or signal_2 = '1' then
signal_out <= '1'
end if;
 
end;