Honored Contributor
Honored ContributorHi,
I got some feedback from the contacted manufacturers and they do (if at all) only provide IBIS models. Thus there seems to be no other option than to write the chip's testbench model on my own. I think this will limit my current efforts in interface simulation validation as e.g. for the stand-alone CAN-Controller I use this might take a lot of time to implement the functions given. My intention was to have the SPI I/F incl. the data evaluation tested by e.g setting a signal in the testbench that would - in real hardware - trigger the interrupt of the CAN-controller, initializing communication and finally resulting in the internal signal "within the FPGA" being set accordingly. For this the CAN-Controller must be first configured by the FPGA to enable the pin as digital I/O, trigger the interrupt on change,.. Maybe this validation has to be done by real hardware tests, either with using SignalTap, a combination of SignalTap and Logic Analyzer to probe the SPI I/F pins or by bringing the result back "out" of the FPGA via Pins, service I/F, ... Well - it is much more work if you want to (or have to) validate operation not only by doing some limited functional tests, but at the end of the day it gives a better "feeling" and trust in the design.
