VHDL Modules for testbench - external Hardware

You will need to contact the manufacturers. SOme provide them on their websites, while some do not. Some probably dont even have the simulation models.

Be prepared for models in Verilog, as thats what most of the models I have seen coded in. So if you have your code in VHDL, you will need a mixed code simulation licence.

Secondly, the IC models will usually be timing models, which are slow and can make functional and debug testing long and laborious. Usually its better just to get hold of your write your own behavioural model at the bus level, rather than the whole chip.

Have a read up on transaction modelling. You can use functions, procedures, protected types and the like to create very fast running simulation models of interfaces. Many of these may already exist in the UVM libraries, so have a look there first (but again, you will probably need a mix mode licence, as UVM is based in SystemVerilog, but Modelsim will give you a VHDL interface to them).

also have a look at this: http://osvvm.org/