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Altera_Forum
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14 years ago

VHDL Math Real & Quartus

I've been using the VHDL package ieee.math_real to declare parameters, the idea being to condense as much information in a design file as possible. in particular, for fixed point operations in feedba...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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What I am / was trying to achieve is completely parameterized code; with no errors or warning messages . . . James

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Right, that was what FVM was getting at. You can clear that particular error by using 'constant RecipFactor' instead of 'variable RecipFactor'.

Cheers,

Dave