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Altera_Forum
Honored Contributor
14 years agoVHDL Math Real & Quartus
I've been using the VHDL package ieee.math_real to declare parameters, the idea being to condense as much information in a design file as possible. in particular, for fixed point operations in feedba...
Altera_Forum
Honored Contributor
14 years agoWhat I am / was trying to achieve is completely parameterized code; with no errors or warning messages . . . James