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Altera_Forum
Honored Contributor
Honored ContributorVHDL Math Real & Quartus
I've been using the VHDL package ieee.math_real to declare parameters, the idea being to condense as much information in a design file as possible. in particular, for fixed point operations in feedba...
Altera_ForumHonored Contributor
Honored ContributorI don't understand what you are trying to achieve. A "variable" to be used for compile time calculations can be defined as a constant.
