[VHDL] integer to std_logic or std_logic_vector conversion

I'm using Cadence NC-VHDL actually... No station with Quartus free right now...

About my process, here is the actual version :

 
conv : PROCESS
VARIABLE reset_hwTemp : unsigned(31 downto 0);
VARIABLE reset_hwVar : std_logic;
VARIABLE wdogInitDelayVar : std_logic_vector(15 downto 0);
BEGIN
if rst_n='0' then
   reset_hwVar := '0';
   reset_hw_o <= '0';
   reset_hwTemp := (others=>'0');
 
    wdogInitDelayVar := (others=>'0');
   wdogInitDelay_o <= (others=>'0');
   WAIT until rst_n='1';
else
   -- Cast an integer to an unsigned on 1 bit and cast it again to std_logic
   --print("Integer read : " & str(reset_hw_i));
   reset_hwTemp := to_unsigned(reset_hw_i, 32);
   reset_hwVar := reset_hwTemp(0);
   --print("std_logic_vector " & str(reset_hwVar));
   --reset_hw_o <= reset_hwVar;
 
   -- Cast an integer to an unsigned on 16 bit and cast it again to    std_logic_vector
   --wdogInitDelayVar := std_logic_vector(to_unsigned(wdogInitDelay_i, 16)); 
   --print("Integer read : 0x" & str(wdogInitDelay_i, 16));
   --print("std_logic_vector 0x" & hstr(wdogInitDelayVar));
   --wdogInitDelay_o <= wdogInitDelayVar;
 
   WAIT until rst_n='1'or (clk'event and clk='1');
end if;

I still have a problem with the line

 
reset_hwTemp := to_unsigned(reset_hw_i, 1);

I've the following error :

 
range constraint violation

If needed, I can always use an if statement on the binary integer to produce std_logic signals, something like

 
IF int_bin=0 THEN
   std_log <='0';
ELSEIF int_bin=1 THEN
   std_log <='1';
ELSE
   assert FALSE
   report "wrong input"

About the second part of the process, I'll try to use the following statement...

 
VARIABLE wdogInitDelayVar : std_logic_vector(15 downto 0);
...
wdogInitDelayVar := to_unsigned(wdogInitDelay_i, 16)(15 downto 0);