[VHDL] integer to std_logic or std_logic_vector conversion

Hello Tricky,

First, thanks for your time and interest...

Next, I indeed though that

signal a: std_logic_vector(0 downto 0);
signal b : std_logic;
b <= a;

was correct. I changed it.

However,

reset_hwVar := to_unsigned(reset_hw_i, 1)(0);

produces an error : "Range constraint violation", whatever the value I store in my text file (0 or 1).

Shouldn't I store it to a temporary value because VHDL doesn't understand the statement?

VARIABLE reset_hwTemp : unsigned(0 downto0);
...
reset_hwTemp:= to_unsigned(reset_hw_i, 1);
reset_hwVar := reset_hwTemp(0); 

(I tried, I've the same error)

What concerns the process, indeed, It will run on every clock event...

Didn't pay attention to it yet. I just put 'WAIT UNTIL' statements.