[VHDL] integer to std_logic or std_logic_vector conversion

Looking at your code, I think you are getting a little confused. Basically, you seem to misunderstand the difference between std_logic and std_logic_vector.

A std_logic_vector is an array of std_logic. Therefore, they are NOT the same type, and you cannot assing a std_logic from a std_logic_vector, but you can assign one from an individual element of a std_logic_vector.

So, in this case:

signal a: std_logic_vector(0 downto 0);

signal b : std_logic;

you cannot do this, even though the length is only 1:

b <= a;

you have to do this:

b <= a(0);

Now, also know that unsigned and signed are also arrays of std_logic, hence why you can do a simple type conversion between them rather than need a conversion function (like to_unsigned) because they are similar type.

So the problem you have is this line:

reset_hwVar := std_logic_vector(to_unsigned(reset_hw_i, 1));

because reset_hwVar is a std_logic (not a vector). To solve this, all you need to do is select the 0th bit of the output of the conversion function to unsigned(because it is an array of std_logic)

so you can change it to this

reset_hwVar := to_unsigned(reset_hw_i, 1)(0);