VHDL integer causing RTL and Gate level simulation difference

zhujianbinc,

you can't avoid using integers to access arrays.

That said, that kind of RTL vs post-synthesis inconsistency is in no way limited to use of integers.

In fact, at least when you're using integers you get warnings like those from the RTL simulation. Other cases may be dead silent.

a <= b when c = '0' else d;

Consider than a, b, c and d are all std_logic and think of how the code behaves when b = 1', c = 'X' and d = '0' .

In RTL, a will be '0'; in post-synthesis it will be 'X'.

Anyway, you can try and make RTL and post-synthesis simulations match better by coding the handling of "X" explicitly when needed.

For example, replace

c <= a(TO_INTEGER(UNSIGNED(b));

with

c <= a(TO_INTEGER(UNSIGNED(b)) when not is_x(b) else 
(others => 'X');

It will synthesize the same, but you'll get XX when b has an X.

PS: This is an Altera forum, people assume you're talking about (Altera) FPGAs here. If you're going to ask about something else, please start by making it crystal clear.