VHDL integer causing RTL and Gate level simulation difference

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Anybody know how to avoid INTEGERs when access arrays?

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Use conversion operators that output an integer.

For example;

type rddata_mux_t is array (0 to 7) of std_logic_vector(31 downto 0);
signal rddata_mux : rddata_mux_t;
signal rddata_sel  : std_logic_vector(2 downto 0);
rddata_mux(0) <= ....
rddata_mux(1) <= ....
rddata <= rddata_mux(to_integer(unsigned(rddata_sel)));

Or as Tricky comments, define a range restricted integer for rddata_sel. However, as you note, you cannot see an 'X' in that case, so using std_logic is a little more general.

Cheers,

Dave