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Our turbo decoder design can pass the RTL simulations, but not the gate level. We have to deposit '0's to all the flops before we can pass gate level simulation. When the chip comes back in our lab, we see some tests passes, but not others. Some chips passes all tests consistently, but others not. If we run some tests first, then other tests starts to pass as well.
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Are you talking about FPGA or ASICs?. As previously explained, FPGA registers have a defined POR state which determines the behaviour in gate level simulation.
It should be noticed however that the problems brought up by asynchronous reset can also affect power-on reset if the design clock is already present during reset. In this case, explicite reset logic and a reset synchronizer are required.
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Uninitialized integers get assigned the value -2^(N-1), where N is the number of bits in the integer. (At least under VHDL).
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This is only true in functional simulation and for unconstrained or signed integers. Integers are synthesized either as signed or unsigned in gate level logic, depending on the range and initialized to all zero by default.
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This is why I want to get rid of all INTEGERs so that I can have a consistently simulation between RTL and GATE. I can capture all my bugs in RTL simulation only.
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The described problems in gate level behaviour have unlikely to do with integer usage.
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