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Altera_Forum
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14 years ago

VHDL integer causing RTL and Gate level simulation difference

I have a general question regarding the use of integers in VHDL. If I have a lot of Array defined, we have to use integer as its index when accessing the arrays. However, when the index is conv...
Altera_Forum's avatar
Altera_Forum
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14 years ago

There is nothing wrong with integers when properly constrained. I'm with KJ - dodgy code and/or testbench.