VHDL integer causing RTL and Gate level simulation difference

OK. Here is what we observed in our lab.

Our turbo decoder design can pass the RTL simulations, but not the gate level. We have to deposit '0's to all the flops before we can pass gate level simulation. When the chip comes back in our lab, we see some tests passes, but not others. Some chips passes all tests consistently, but others not. If we run some tests first, then other tests starts to pass as well.

All of these observations made us think there is initialization issues in our design. Since we decided not to do reset to all of our flops unless required. There is lots of flops not having known reset value at power on.

My task is to figure our what needs to be reset in this design. Since there is lots of integers used in the design, such as index to arrays and integers get value '0' at power on in RTL simulation, while it gets unknown value in real chip. This, I think, made RTL simulation hides lot of potential bugs in our design.

This is why I want to get rid of all INTEGERs so that I can have a consistently simulation between RTL and GATE. I can capture all my bugs in RTL simulation only.