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Altera_Forum
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13 years ago

VHDL integer causing RTL and Gate level simulation difference

I have a general question regarding the use of integers in VHDL. If I have a lot of Array defined, we have to use integer as its index when accessing the arrays. However, when the index is conv...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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In general, we don't want to give an initial value to a variable since it is ignored by the synthesize tools.

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What makes you say that?

FPGAs configure from bit-streams, and those bitstreams define the register states at power-on. Most devices power-up with registers set to 0, but if you initialize a signal to 1, the synthesis tool will use 'not gate pushback' to invert the input and output to the register, so as far as your logic is concerned, the register powers up to your initialized value of 1.

Cheers,

Dave